The present invention relates to a data processing circuit arranged to execute program instructions defining nested loops, wherein a loop is defined in terms of start address, an end address and a number of loop iterations.
The use of nested loops in the software arts is well established. Nested loops allow a relatively small amount of code to control a relatively large amount of processing and major advantages are obtained from software implementations by making use of a processor's ability to execute relatively simple operations many times in a reliable way. The nested loop approach is made possible by the inclusion of conditional jumps such that the processor is instructed as to when a loop has terminated.
Problems may occur when a condition which allows an inner loop to terminate also allows its associated outer loop to terminate. Under these conditions, a program counter may have been incremented, in response to completing the inner loop, without leaving sufficient time for the outer loop to terminate. When such a condition arises, the operation of the hardware causes an unintentional change in the program counter which causes the program to enter an unintended state, often resulting in system failure.
Hitherto, problems such as this have been addressed by including a "no-operation" (NOP) instruction before the terminating condition for the outer loop.